module sim12(input clk, reset );

  wire [7:0] pc, address;
  wire [11:0] ibus, Ain, DataOut;
  wire memwrite;
  
  // instantiate processor and memories
  sim12_dp dp(clk, reset, ibus, pc, memwrite, address, Ain, DataOut);
  sim12_imem imem(pc, ibus);
  sim12_mem mem(clk, memwrite, address, Ain, DataOut);
     
endmodule

